1) Field of the Invention
The present invention relates to image information apparatuses such as digital copying machines, facsimile apparatuses, printers, scanners, network file servers, and digital multifunction products.
2) Description of the Related Art
Considerable progress has been made in recent years in the information processing related technology. Similarly, remarkable improvement has been made in the data transfer rates of large capacity storages, and the data compression ratios and the processing speeds of data compressing units.
It has become common to connect, as secondary storages, large and high-speed capacity storages to image information apparatuses. When such secondary storages are provided, it becomes possible to employ a configuration capable of inputting and outputting a plurality of image data in parallel. However, in this case, how efficiently the processing for storing (writing) image data in and reading image data from the secondary storage is performed becomes an important factor that decides the processing efficiency.
Assume that a variety of image inputting and outputting units are connected to an image information apparatus. In this case, it is difficult with the conventional memory control to maintain the processing efficiency by making the most of abilities of the secondary storage and the data compressing unit. One approach to solve this problem is to use a memory control system that employs a DMA for managing acquisition and release of resources for realizing maximum efficiency of use according to a processing ability of the secondary storage.
Precisely, in the conventional technique disclosed in Japanese Patent No. 2,950,962, images on a front side and a back side of an original are read in parallel, the image data of the front side and the image data of the back sides are connected by a unit of one line and stored in a buffer memory. The connected image data are separated into image data on the front side and image data on the back side when outputting the image data to the next stage. On the other hand, the image data can be output to the next stage as is, i.e., without separating.
Moreover, in the conventional technique disclosed in Japanese Patent Application Laid-open No. 2002-135544, images on a front side and a back side of an original are read in parallel, the image data of the front side and the image data of the back side are connected by a unit of one line. The connected image data is stored in a buffer memory (image memory), and simultaneously, read out and directly transferred to a hard disk. As a result, transfer of the image data to the hard disk can be started before writing of the image data in the buffer memory ends.
FIG. 10B is an example of a structure of a conventional digital multifunction product. In this digital multifunction product, image data on a front side and a back side of an original are respectively transferred to a secondary storage in parallel through, for example, a peripheral component interconnect (PCI) bus. Precisely, each of image input devices 133 and 134, which can be CCDs, read images on the front side and the back side of the original in parallel. The image data on the front side is stored in a frame memory 135a and the image data on the back side is stored in a frame memory 135b. 
A transfer unit 162 reads out, via a selector 161, a predetermined amount of image data from the frame memory 135a with a delay of, for example, a predetermined time from the start of reading of the images by the image input devices 133 and 134, and passes the read image data to a PCI transfer controller 152. The PCI transfer controller 152 transfers the image data to a primary storage (which can be a semiconductor memory) 116 through a PCI bus. Next, the transfer unit 162 reads out, via the selector 161, a predetermined amount of image data from the frame memory 135b, and passes the image data to the PCI transfer controller 152. The PCI transfer controller 152 transfers the image data to the primary storage 116 through the PCI bus. Thus, the transfer unit 162 first transfers the image data from the frame memory 135a to the PCI transfer controller 152 and then repeats the processing for transferring the image data from the frame memories 135a and 135b to the PCI transfer controller 152 alternately.
Thus, in the conventional technique, the image data from the frame memory 135a is transferred first to the PCI transfer controller 152. Therefore, although the image data from the frame memory 135b is ready for transfer, if the image data from the frame memory 135a is not ready for transfer, transfer of the image data is not stated. In other words, although the PCI transfer controller can process transfer requests from plural request sources in parallel, the function is not fully utilized.
Thus, in the conventional techniques, most of the functions (parallel reading, reading speed, output speed, etc.) of the image input/output units are not fully used.
For example, when image reading units, which are capable of reading image data on both sides of an original in parallel, transfer the image data on the front and the back sides to a secondary storage side, the image reading units often transfer the image data read from the front and the back sides to the secondary storage sequentially for each side. This is because, although processing of image data is improved compared with that in the past, depending on a combination of image input/output units that execute processing for transferring image data to, storing image data in, and readout image data from the secondary storage side simultaneously, it is difficult to process plural image data in parallel because of a problem of speed.
However, taking into account freedom of structure, extension, and the like of an image information apparatus, a data transfer unit like a universal serial bus (USB) or a PCI is often used for a data transfer (transmission and reception) unit for inputting and outputting image data to and from the secondary storage side such that transfer of plural data can be executed by an identical transfer unit (e.g., the PCI transfer controller described above) simultaneously (in parallel). Under such circumstances, it is inevitable to transfer plural image data between the image information apparatus and the secondary storage in parallel.